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Chapter 15: Arithmetic Library
Table 15–21. DSP Block I/O Formats
(1)
15–15
,
I/O
Simulink
(2) (3)
VHDL
Type
(4)
O
O1 2 x [L1] + ceil(log2(n)) .2
O1: out STD_LOGIC_VECTOR({(2 x L1) + ceil(log2(n)) + (2 x R1) - 1} DOWNTO 0) Implicit
x [R1]
Notes to Table 15–21 :
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
(3) I1 [L].[R] is an input port. O1 [L].[R] is an output port.
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
Figure 15–8 shows an example of a basic low-pass filter with two DSP blocks.
Figure 15–8. DSP Block Example
Gain
The Gain block generates its output by multiplying the signal input by a specified
gain factor. You must enter the gain as a numeric value in the Gain block parameter
field. The gain factor must be a scalar.
1
The Simulink software also provides a Gain block. If you use the Simulink Gain block
in your model, you can use it only for simulation; Signal Compiler cannot convert it to
HDL.
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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